Custom Waveform Generators
- The Dave Lawton 9XA
- 50% Duty Cycle Double Frequency Generator
- Adjustable Duty Cycle Gated Pulse Frequency
- 9XA Method
- 2 Arduino - Dual Channel - Triple AND Gate (Perfect Pulse Driver)
The Dave Lawton 9XA
Source: http://quanthomme.free.fr/qhsuite/2011News/imagenews11/MeyerReplicatAnglais29pages.pdf
The Dave Lawton 9XA is a versatile pulse and gate generator with variable duty cycle on both 555 timers.
One design note that exists here, is that Pin 3 Output of timer 1 is used to provide Vcc power to Pin 4 on Timer 2. This means an inherent latency is always introduced by the 1st RC charge cycle to power up the 2nd timer. This would cause a partial leading pulse. Other than that issue, it's a pretty solid circuit.
Using a BUZ350 mosfet to pull down the B+ 12V through the cell and negative choke.
50% Duty Cycle Double Frequency Generator
PDF Download: http://irondmax.com/pdf/ProjectIcarus.pdf
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50% Duty Cycle Generator |
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50% Duty Cycle Divide X 10 |
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Gated Frequency |
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Signal Inverter |
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5 Volt Regulator |
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Clock Pulse Generator |
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Adjustable Duty Cycle Gated Pulse Frequency
One can use a 555 with two 1N4148 diodes to allow independent control of duty cycle ON/OFF times. Each diode has a 100k 10-turn precision potentiometer placed in series to capacitor as shown below. Rotary switch for selection of different capacitor values can allow frequency range selectivity. "RA" below can be a potentiometer to allow for frequency adjustment.
Photo from Electronic Tutorials: Electronic Tutorials (555)
In the build below, pin 3 of 555 was also output to CD4017 decade counter stage to produce a gate. This provided clock synchronization, and only allows 5 pulses per gate ON time. Otherwise, any independent driver of CD4017 would produce clock drift and not allow a discrete number of pulse per gate ON time. Beauty of shift registers in 4017's is even though a 1mS ON time may be occurring, the whole period will be used to divide by 10. Thus maintaining a 50% gated pulse time if desired. Both the adjusted pulse train from Pin #3 and output of CD4017 (Pin #12) is put into inputs (Pin #1 and Pin #2) of a 7408 AND logic gate chip. Pin #3 on 7408 is output, which is shown in yellow below on scope. Circuit driver side isolation may be achieved with H11D1 similar to the 9XA.
Gate can be adjusted by RA resistor to produce increase occurrences of pulse train
Pulse duty cycle ON time, down to lowest, measured at 1mS.
Adjustable Gated Pulse Freq Gen
This method allows pulse duty cycle control, and synchronized gate to pulse train.
9XA Method
The 9XA was a circuit that Stan used to produce a gated pulse frequency via two H11D1 optocouplers. The optocouplers were driven by two independent stages of 555 timer clock frequency into 3 7490 decade counter ICs. The 7490s provided divisions of 555 frequency, but also produced 50% duty cycle pulses. Below, "A" is one 555/7490 stage and "B" is second 555/7490 stage. The two optocouplers produce an equivalent to AND logic gate.
Figure 1: 9XA schematic
Below is an 9xa scope shot, showing how two independent 9XB style frequency generator's outputs were used to trigger two H11D1 optocouplers to produce a gated pulse train as shown in schematic. In this setup, I had 555's produce a 100khz output to 4 CD4017 dividers. This allowed a 10khz with 50/50 duty cycle to be achieved. LED is just for visual confirmation. If looking closely, you can see how the gating generator isn't synchronized with frequency generator. This causes extra pulses to arise during gated ON times, also called "clock drift".
NOTE: CD4017s were used in place of 7490s, they accomplish the same task with less wiring required.
Video Link: 9XA Circuit Waveform
2nd setup had a modification where both signals from 555/CD4017 were fed into an 7408 AND logic gate. This produced the waveform seen below. In this instance, only 1 H11D1 optocoupler was required.
LED providing visual verification of pulse waveform.
