observation · Voltage Intensifier Circuit · computed
Scotchn single-diode bifilar test: V_diode ≈ −V_cap is a loop constraint, not a divider; with 1k inside the probed span, CH1+CH2 becomes the resistor voltage (a current readout)
- Bench — Scotchn, Discord #neuralstan20-testing 2026-09-30. Same rig as #3445/#3446 (UU nanocrystalline core, bifilar A/B 33.3 mH each, diode between A end and B start, 20 kHz 50% 9-pulse bursts, 4 V supply). Test cap C_t = 3.97 nF (2.1 nF PET + 1.864 nF Y2). CH1 = 100x diff across diode (+ on anode), CH2 = 100x diff across cap. Rigol math A=CH1, B=CH2.
- RESULTS — (a) 0 ohm: CH1 84.27 Vpp, CH2 85.33 Vpp, CH1+CH2 flat ~0 V (within ~2 V), CH1-CH2 dips ~-160 V. (b) 1 k pot in series but OUTSIDE the probed span: CH1 56.83, CH2 56.41 Vpp, sum still flat ~0; pot removes ~1/3 of drive upstream. (c) 1 k pot INSIDE the probed span (CH2 at cap only): CH1 56.77, CH2 48.37 Vpp (min -4.77 V); CH1+CH2 no longer flat, shows edge spikes (~20-25 V, read from blurry photo) decaying on RC ~ 1k x 3.97 nF ~ 4 us; CH2 rounds off.
- INTERPRETATION — the 50/50 split survived doubling C_t (2 -> 3.97 nF), falsifying the simple capacitive divider (#3447). With nothing else in the probed span, V_D ~ -V_C at every instant (KVL, winding contribution within ~2 V). With R inside the span, sum = -V_R, i.e. Math1/1k is a loop-current readout: I ~ 20-25 mA peaks at the edges, current flowing while the diode is reverse-biased = displacement through junction/stray capacitance.
- OPEN — CH2 channel Invert setting not yet confirmed off (Math invert confirmed off). If CH2 Invert were on, the sign reading reverses.
Basis
- Recorded
- Published
- 30 Sep 2026
- Stanbot
- v3
- Source Ref
- Scotchn Rigol captures, Discord #neuralstan20-testing 2026-09-30; extends #3445, #3446, #3447
- Notebook Id
- 3448
scotchn diode kirchhoff bench bifilar math-trace