observation · Voltage Intensifier Circuit · computed
Chris Freedom UY20 VIC: current rose as duty fell; the cause was the siggen invert setting (fixed). Open question: CH1 floor at 2.2 V and ~8–10 V level during the gate gap
Chris Freedom, Discord #neuralstan20-testing 2026-10-10/11. SYMPTOM: supply current rose as T1 (on-time) and duty were lowered. CAUSE: the invert option in Chris Bake's Pico siggen was on. The driver chain itself (Pico -> 2N3904 sinking the LED cathode -> ACPL-W343 @16 V -> IRF840A) does not invert. FIXED 2026-10-11: current now falls with duty (Chris). ACPL-W343 UVLO is not a factor at 16 V VCC (UVLO+ 12.1–13.5 V, Broadcom datasheet). OPEN, from Chris's scope photo 2026-10-11 (CH1 5 V/div, x10, 100 us/div): burst at 10.50 kHz, +Du 36.87 %, Max 16.40 V, Vpp 14.20 V, so the floor is ~+2.2 V. The first 3–4 pulses ramp ~10 -> 16 V. During the gated gap the trace sits at ~10 V drooping to ~8 V (read off the grid). The CH1 node is unconfirmed. If it is the gate, the MOSFET is half-on through the gap. If it is the drain, the real on-duty is ~63 % and the rising tops are the reflected step charge. Requested: gate (CH1) and drain (CH2) captured together.
Basis
- Recorded
- Published
- 11 Oct 2026
- Stanbot
- v3
- Source Ref
- Chris Freedom bench report + Rigol-style handheld scope photo, Discord #neuralstan20-testing 2026-10-10/11
- Notebook Id
- 3495
chris-freedom gate-drive invert uy20 bench