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Parasitic Effects

Parasitic Capacitance & SRF

Real inductors have parasitic capacitance between turns and layers that limits their useful frequency range. Understanding these effects is critical for VIC design, as they determine the maximum operating frequency and affect circuit tuning.

Sources of Parasitic Capacitance

Parasitic capacitance in inductors comes from several sources:

1. Turn-to-Turn Capacitance (Ctt)

Capacitance between adjacent turns in the same layer. Depends on wire spacing and insulation.

2. Layer-to-Layer Capacitance (Cll)

Capacitance between winding layers. Often the largest contributor in multi-layer coils.

3. Winding-to-Core Capacitance (Cwc)

Capacitance between the winding and the magnetic core (if conductive or grounded).

4. Winding-to-Shield Capacitance

In shielded inductors, capacitance to the external shield.

Self-Resonant Frequency (SRF)

The parasitic capacitance resonates with the inductance at the Self-Resonant Frequency:

SRF = 1 / (2π√(L × Cparasitic))

Behavior at SRF:

  • Impedance is maximum (parallel resonance)
  • Inductor is neither inductive nor capacitive
  • Phase angle crosses through 0°

Above SRF:

The "inductor" behaves as a capacitor! Impedance decreases with frequency.

Impedance vs. Frequency

    |Z|
     ↑
     │                    ╱╲
     │                   ╱  ╲     ← Peak at SRF
     │                  ╱    ╲
     │                 ╱      ╲
     │               ╱         ╲
     │             ╱            ╲
     │           ╱               ╲
     │         ╱                  ╲
     │       ╱                     ╲
     │     ╱                        ╲
     │   ╱   Inductive region        ╲ Capacitive region
     │ ╱      |Z| = 2πfL              ╲ |Z| = 1/(2πfC)
     └────────────────────────────────────────────→ f
                          SRF

    Phase:  +90° ───────────┬─────────── −90°
                           0° (at SRF)

Operating Frequency Guidelines

fop / SRF Behavior Recommendation
< 0.1 (< 10%) Nearly ideal inductor Preferred range
0.1 - 0.3 (10-30%) Slight inductance increase Acceptable with correction
0.3 - 0.7 (30-70%) Significant deviation Caution - Q drops
> 0.7 (> 70%) Near or past SRF Do not use

Effective Inductance Near SRF

As frequency approaches SRF, the apparent inductance increases:

Leff = Ldc / [1 - (f/SRF)²]

Example:

  • Ldc = 10 mH, SRF = 100 kHz
  • At 30 kHz: Leff = 10 / [1 - 0.09] = 11.0 mH (+10%)
  • At 50 kHz: Leff = 10 / [1 - 0.25] = 13.3 mH (+33%)
  • At 70 kHz: Leff = 10 / [1 - 0.49] = 19.6 mH (+96%)

Minimizing Parasitic Capacitance

Winding Techniques:

  1. Single-layer winding: Eliminates layer-to-layer capacitance
  2. Space-wound turns: Increases turn-to-turn distance
  3. Honeycomb/basket winding: Crosses turns to reduce adjacent voltage
  4. Bank winding: Winds in sections to reduce voltage across layers
  5. Progressive winding: Keeps voltage gradient low between adjacent turns

Design Choices:

  • Use fewer turns (requires higher permeability core)
  • Use thinner insulation (but watch voltage ratings)
  • Use air-core (eliminates winding-to-core capacitance)
  • Choose toroidal cores (natural progressive winding)

Calculating Parasitic Capacitance

Turn-to-Turn Capacitance (Simplified)

Ctt ≈ ε₀εr × lturn × dwire / s

Where s is the spacing between adjacent turn centers.

Layer-to-Layer Capacitance

Cll ≈ ε₀εr × Alayer / tinsulation

Where Alayer is the overlapping area between layers.

Total Parasitic Capacitance

The total equivalent capacitance is complex because the distributed capacitances see different voltages. For a rough estimate:

Cparasitic ≈ Cll/3 + Ctt/N

The 1/3 factor accounts for voltage distribution across layers.

Measuring SRF

Method 1: Impedance Analyzer

  1. Connect inductor to impedance analyzer
  2. Sweep frequency and plot |Z|
  3. SRF is where impedance peaks

Method 2: Signal Generator + Oscilloscope

  1. Connect inductor in series with known resistor
  2. Drive with sine wave, sweep frequency
  3. Monitor voltage across inductor
  4. SRF is where voltage peaks (current minimum)

Method 3: Resonance with Known Capacitor

  1. Measure inductance at low frequency
  2. Add known capacitor in parallel
  3. Find new resonant frequency
  4. Calculate parasitic C from the difference

SRF in VIC Design

Problem Symptom Solution
Operating too close to SRF Resonance frequency higher than calculated Reduce tuning cap or use different choke
Operating above SRF No resonance, circuit acts capacitive Must redesign with fewer turns
Low SRF in bifilar winding Limited usable frequency range Accept limitation or use separate chokes

VIC Matrix Calculator: The Choke Design module estimates SRF based on winding geometry and displays a warning if your operating frequency is too close to SRF. It also calculates the effective inductance at your operating frequency.

Next: DC Resistance and Q Factor →

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